Self Controllable Pass Transistor Low Power Pulsed Flip-Flop
نویسندگان
چکیده
In this paper, a novel low power pulsed flip-flop (PFF) using self-controllable pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. In the D to Q path inverter is removed and the transistor is replaced with pass transistor logic. The pass transistor is driven by generated clock pulse is used directly to drive the flip flop output. The presented design is compared with the SCCER and low-power pulse triggered flip-flop with conditional pulse enhancement (LPFFCE) scheme. As compared to the SCCER, LPFF-CE the proposed pulsed flip-flop (PFF) design features best speed, power. The proposed technique is implemented using TSPICE CMOS 180nm technology. The average power consumption for proposed design is reduced compared with the conventional flip flops. Keywords— Low power, pulsed flip-flop, pass transistor logic, critical path, self-controllable, power.
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